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A25LQ64 series 64m-bit ( x1 / x2 / x4) 3.3v cmos mxsmio (serial multi i/o) flash memory (july, 2014, version 1.4) amic technology corp. document title 64m-bit ( x1 / x2 / x4) 3 .3 v cmos mxsmio (serial multi i/o) flash memory revision history rev. no. history issue date remark 0.0 initial issue june 2, 2012 preliminary 0.1 add 16-pin sop (300mil) package type june 28, 2012 0.2 add 8-pin sop (209mil) package type july 10, 2012 0.3 add fast read dual output (3bh) command november 1, 2012 0.4 refine qe bit definition to control only hardware protect function november 19, 2012 0.5 change figure-36-1, 36-2 and refine erase cycling january 14, 2013 1.0 final version release march 5, 2013 final 1.1 sfdp address 08h id code 37 changed to 00 may 9, 2013 sfdp address 38h & 4ah eb dummy code data bits 04~00 changed from 00110b to 00100b 1.2 add A25LQ64m-fe type in ordering information july 01, 2013 this type fixes qe bit ?1? the hardware protect function is disabled in this type add 8-pin dip package type 1.3 modify the fast program time spec. january 9, 2014 1.4 change figure 7. unique id to 64 bytes july 3, 2014
A25LQ64 series 64m-bit ( x1 / x2 / x4) 3.3v cmos mxsmio (serial multi i/o) flash memory (july, 2014, version 1.4) 1 amic technology corp. features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 64mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two i/o mode) structure or 16,777,216 x 4 bits (four i/o mode) structure ? equal sectors with 4k byte each, or equal blocks with 32k byte each or equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to v cc +1v ? low v cc write inhibit is from 2.2v to 2.4v performance ? high performance - fast read for spi mode - 1 i/o: 104mhz with 8 dummy cycles - 2 i/o: 84mhz with 4 dummy cycles, equivalent to 168mhz - 4 i/o: 104mhz with 2+4 dummy cycles, equivalent to 416mhz - fast read for qpi mode - 4 i/o: 84mhz with 2+2 dummy cycles, equivalent to 336mhz - 4 i/o: 104mhz with 2+4 dummy cycles, equivalent to 416mhz - fast program time: 0.3ms (typ.) and 0.8ms (max./10k)/ 2ms (max./100k) /page (256-byte per page) - byte program time: 6 s (typical) - 8/16/32/64 byte wrap-around burst read mode - fast erase time: 40ms (typ.)/sector (4k-byte per sector); 80ms (typ.)/block (32k-byte per block), 120ms (typ.) / block (64k-byte per block); 12s(typ.) /chip ? low power consumption - low active read current: 25ma (max.) at 104mhz, 20ma (max.) at 84mhz - low active erase/programming current: 20ma (typ.) - standby current: 2 a (typ.) ? deep power down: 2 a(typ.) ? typical 100,000 erase/program cycles ? 10 years data retention software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defines the size of the area to be software protection against program and erase instructions - additional 4k-bit secured otp - 1k bit sfdp serial flash definition parameter - 64 bytes unique id for each device ? auto erase and auto program algorithm - automatically erases and verifies data at selected sector or block - automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programmed should have page in the erased state first) ? status register feature ? command reset ? program/erase suspend ? electronic identification - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems command for 1-byte manufacturer id and 1-byte device id ? when using A25LQ64m-fe, the hardware protected mode (hpm) is disabled hardware features ? serial clock (c) - serial clock input ? di (io 0 ) - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? do (io 1 ) - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? w (io 2 ) - hardware write protection or serial data input/output for 4 x i/o read mode ? io 3 - serial input & output for 4 x i/o read mode ? package - 8-pin dip (300mil), 8-pin sop (209mil), 16-pin sop (300mil), 8-pin wson (6*5mm) or 24-ball bga (6*8mm) - all pb-free (lead-free) products are rohs2.0 compliant
A25LQ64 series (july, 2014, version 1.4) 2 amic technology corp. general description A25LQ64 is 67,108,864 bits serial flash memory, which is configured as 8,388,608 x 8 internally. when it is in two or four i/o mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. A25LQ64 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single i/o mode. the three bus signals are a serial clock (c), a serial data input (di), and a serial data output (do). serial access to the device is enabled by s input. when it is in two i/o read mode, the di pin and do pin become io 0 pin and io 1 pin for address/dummy bits input and data output. when it is in four i/o read mode, the di pin, do pin and w pin become io 0 pin, io 1 pin, io 2 pin and io 3 pin for address/dummy bits input and data output. after program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4k-byte), block (32k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and s is high, it is put in standby mode and draws less than 10 a dc current. table 1. additional feature comparison read performance protection and security spi qpi additional features part name flexible block protection (bp0-bp3) 4k-bit security otp 1 i/o (104 mhz) 2 i/o (84 mhz) 4 i/o (84 mhz) 4 i/o (104 mhz) 4 i/o (84 mhz) 4 i/o (104 mhz) A25LQ64 v v v v v v v v identifier additional features part name res (command: ab hex) rems (command: 90 hex) rdid (command: 9f hex) qriid (command: af hex) A25LQ64 16 (hex) 37 16 (hex) (if add=0) 37 40 17 37 40 17
A25LQ64 series (july, 2014, version 1.4) 3 amic technology corp. pin configuration ? 8-pin dip / sop ? 16-pin sop ? 8-pin wson v cc c s w (io 2 ) io 3 v ss 1 8 2 7 3 6 4 5 A25LQ64 do (io 1 ) di (io 0 ) A25LQ64 1 2 3 4 8 7 6 5 do (io 1 ) s w (io 2 ) v ss v cc c di (io 0 ) io 3 v cc c nc do (io 1 ) s io 3 v ss 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 A25LQ64 nc nc nc di (io 0 ) nc nc nc nc w (io 2 ) ? 24-ball bga a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 e1 e2 e3 e4 f1 f2 f3 f4 nc nc nc nc nc c v ss v cc nc snc w (io 2 ) nc do (io 1 )di (io 0 )io 3 nc nc nc nc nc nc nc nc top view, balls facing down
A25LQ64 series (july, 2014, version 1.4) 4 amic technology corp. pin descriptions pin name description s chip select di (io 0 ) serial data input (for 1 x i/o) / serial data input & output (for 2 x i/o or 4 x i/o read mode) do (io 1 ) serial data output (for 1 x i/o) / serial data input & output (for 2 x i/o or 4 x i/o read mode) c serial clock w (io 2 ) write protection: connect to v ss or serial data input & output (for 4 x i/o read mode) io 3 serial data input & output (for 4 x i/o read mode) v cc + 3.3v power supply v ss ground nc no connect block diagram address generator di (io 0 ) s w (io 2 ) io 3 c do (io 1 ) sram buffer mode logic clock generator state machine hv generator sense amplifier output buffer y-decoder memory array page buffer x-decoder data register
A25LQ64 series (july, 2014, version 1.4) 5 amic technology corp. data protection the A25LQ64 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transition or system noise. ? power-on reset and t puw : to avoid sudden power switch by system power supply transition, the power-on reset and t puw (internal timer) may protect the flash. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase 32kb (be32k) command completion - block erase (be) command completion - chip erase (ce) command completion - program/erase suspend - softreset command completion - write security register (wrscur) command completion ? deep power down mode: by entering deep power down mode, the flash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res) and softreset command. ? block lock protection and additional 4k-bit secured otp: there are block protection and 4k secured otp which protect content from inadvertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area definition is shown as table of "protected area sizes", the protected areas are more flexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of "protected area sizes". - the hardware protected mode (hpm) use w (io 2 ) to protect the (bp3, bp2, bp1, bp0) bits and status register write protect bit. when using A25LQ64m-fe, the hardware protected mode (hpm) is disabled. - in four i/o and qpi mode, the feature of hpm will be disabled
A25LQ64 series (july, 2014, version 1.4) 6 amic technology corp. table 2. protected area sizes status bit protect area bp3 bp2 bp1 bp0 64mb 0 0 0 0 0 (none) 0 0 0 1 1 (2 blocks, block 126th~127th) 0 0 1 0 2 (4 blocks, block 124th~127th) 0 0 1 1 3 (8 blocks, block 120th~127th) 0 1 0 0 4 (16 blocks, block 112th~127th) 0 1 0 1 5 (32 blocks, block 96th~127th) 0 1 1 0 6 (64 blocks, block 64th~127th) 0 1 1 1 7 (128 blocks, all) 1 0 0 0 8 (128 blocks, all) 1 0 0 1 9 (128 blocks, all) 1 0 1 0 10 (128 blocks, all) 1 0 1 1 11 (128 blocks, all) 1 1 0 0 12 (128 blocks, all) 1 1 0 1 13 (128 blocks, all) 1 1 1 0 14 (128 blocks, all) 1 1 1 1 15 (128 blocks, all) ii. additional 4k-bit secured otp : to provide 4k-bit one-time program area - which may be locked by customer through wrscur comma nd. the address range and size please refer to table 3. 4k-bit secured otp definition. - security register bit 1 (ldso) indicates whether the 4k-bit secured otp is locked or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enter security otp command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exit security otp command. - customer may lock-down the customer lockable secured otp by writing wrscur (write security register) command to set bit 1 (ldso) as "1". please refer to table 8. security register definition for security register bit definition. - note: once lock-down by ldso bit, it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed. table 3. 4k-bit secured otp definition sector size address range 4096 bit xxx000 ? xxx1ff
A25LQ64 series (july, 2014, version 1.4) 7 amic technology corp. memory organization table 4. memory organization (64mb) block (64k-byte) block (32k-byte) sector (4k-byte) address range 2047 7ff000h 7fffffh ? 255 2040 7f8000h 7f8fffh 2039 7f7000h 7f7fffh ? 127 254 2032 7f0000h 7f0fffh 2031 7ef000h 7effffh ? 253 2024 7e8000h 7e8fffh 2023 7e7000h 7e7fffh ? 126 252 2016 7e0000h 7e0fffh 2015 7df000h 7dffffh ? 251 2008 7d8000h 7d8fffh 2007 7d7000h 7d7fffh ? 125 250 2000 7d0000h 7d0fffh ????.? 47 02f000h 02ffffh ? 5 40 028000h 028fffh 39 027000h 027fffh ? 2 4 32 020000h 020fffh 31 01f000h 01ffffh ? 3 24 018000h 018fffh 23 017000h 017fffh ? 1 2 16 010000h 010fffh 15 00f000h 00ffffh ? 1 8 008000h 008fffh 7 007000h 007fffh ? 0 0 0 000000h 000fffh
A25LQ64 series (july, 2014, version 1.4) 8 amic technology corp. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next s falling edge. in standby mode, do pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next s rising edge. 4. input data is latched on the rising edge of serial clock (c) and data shifts out on the falling edge of serial clock (c). the difference of serial mode 0 and mode 3 is shown as figure 1. "serial modes supported". 5. for the following instructions: rdid, rdsr, rdscur, read, fast read, 2read, 4read, res, rems, qpiid, the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the s can be high. for the following instructions: wren, wrdi, wrsr, se, be32k, be, ce, pp, 4pp, dp, enso, exso, wrscur, suspend, resume, nop, rsten, rst, eqio, rstqio the s must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglected and not affect the current operation of write status register, program, erase. figure 1. serial modes supported msb msb c c di do 00 1 1 cpol cpha mode 0 mode 3 shit in shit out note: cpol indicates clock polarity of serial master, cpol=1 for serial clock (c) high while idle, cpol=0 for serial clock (c) low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported.
A25LQ64 series (july, 2014, version 1.4) 9 amic technology corp. quad peripheral interface (qpi) read mode qpi protocol enables user to take full advantage of quad i/o serial flash by providing the quad i/o interface in command cycles, address cycles and as well as data output cycles. enable qpi mode (eqio) by issuing 35h command, the qpi mode is enable. figure 2. enable qpi sequence (command 35h) s c io 0 io[3:1] 01 23 45 67 35h mode 3 mode 0 quad peripheral interface (qpi) operation to use qpi protocol, the host drives s low then sends the fast read command, 0bh, followed by 6 address cycles and four dummy cycles. most significant bit (msb) comes first, as shown in figure 3. after the dummy cycle, the quad peripheral interface (qpi) flash memory outputs data on the falling edge of the serial clock (c) signal starting from the specified address location. the device continually streams data output through all addresses until terminated by a low-to-high transition on s . the internal address pointer automatically increases until the highest memory address is reached. when reached the highest memory address, the address pointer returns to the beginning of the address space. figure 3. high-speed read sequence (qpi) (command 0bh) 0123 567 4891011131415 12 16 17 18 s c io[3:0] 0b a5 a3 a4 a2a1a0xxxxh0l0h1l1h2l2h3l3 data in msb data out mode 3 mode 0 mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 10 amic technology corp. read data bytes at higher speed by dual output (fast read dual output) the fast read dual output (3bh) instruction is similar to the fast read (0bh) instruction except the data is output on two pins, io 0 and io 1 , instead of just do. this allows data to be transferred from the A25LQ64 at twice the rate of standard spi devices. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possible frequency of f c (see ac characteristics). this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 4. the dummy clocks allow the device?s internal circuits additional time for setting up the initial address. the input data during the dummy clocks is ?don?t care?. however, the io 0 and io 1 pins should be high-impedance prior to the falling edge of the first data out clock. figure 4. fast read dual output instruction sequence and data-out sequence instruction (3bh) high impedance msb 810 9 01 234 5 6 7 24-bit address 28 29 30 31 23 22 21 3 210 7 0 s c di s c 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte msb 1 msb 7 5 31 75 3 msb 7 5 31 75 3 1 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 data out 1 data out 2 data out 3 data out 4 dio switches from input to output do di do note: address bit a23 is don?t care, for A25LQ64
A25LQ64 series (july, 2014, version 1.4) 11 amic technology corp. reset qpi mode (rstqio) by issuing f5h command, the device is reset to 1-i/o spi mode. figure 5. reset qpi mode (command f5h) s c io[3:0] f5 fast qpi read mode (fastrdq) to increase the code transmission speed, the device provides a "fast qpi read mode" (fastrdq). by issuing command code ebh, the fastrdq mode is enable. the number of dummy cycle increase from 4 to 6 cycles. the read cycle frequency will increase from 84mhz to 104mhz. figure 6. fast qpi read mode (fastrdq) (command ebh) 0123 567 4891011131415 12 16 17 18 s c eb a5 a3 a4 a2 a1 a0 x x x x h0 l0 h1 l1 h2 l2 h3 l3 data in msb data out 19 20 xx io[3:0] mode 3 mode 0 mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 12 amic technology corp. command description table 5. command set read commands i/o 1 1 1 1 2 2 read mode spi spi spi spi spi spi command (byte) read (normal read) fast read * (fast read data) sfdp unique id 2read (2 x i/o read command) note1 fast read daul output * (fast read data) clock rate (mhz) 66 104 104 104 84 104 1st byte 03 (hex) 0b (hex) 5a (hex) 4b (hex) bb (hex) 3b (hex) 2nd byte ad1(8) ad1(8) ad1 (8) dummy (8) ad1(4) ad1(8) 3rd byte ad2(8) ad2(8) ad2 (8) dummy (8) ad2(4) ad2(8) 4th byte ad3(8) ad3(8) ad3 (8) dummy (8) ad3(4) ad3(8) 5th byte dummy(8) dummy(8) dummy (8) dummy(4) dummy(8) action n bytes read out until s goes high n bytes read out until s goes high n bytes read out until s goes high n bytes read out until s goes high n bytes read out by 2 x i/o until s goes high n bytes read out by 2 x i/o until s goes high 4 4 4 4 spi spi qpi qpi w4read 4read * (4 x i/o read command) note1 fast read * (fast read data) 4read * (4 x i/o read command) note1 84 104 84 104 e7 (hex) eb (hex) 0b (hex) eb (hex) ad1(2) ad1(2) ad1(2) ad1(2) ad2(2) ad2(2) ad2(2) ad2(2) ad3(2) ad3(2) ad3(2) ad3(2) dummy(4) dummy(6) dummy(4) dummy(6) quad i/o read with 4 dummy cycles in 84mhz quad i/o read with 6 dummy cycles in 104mhz quad i/o read with 4 dummy cycles in 104mhz quad i/o read with 6 dummy cycles in 104mhz
A25LQ64 series (july, 2014, version 1.4) 13 amic technology corp. program/erase commands command (byte) wren* (write enable) wrdi * (write disable) rdsr * (read status register) wrsr * (write status register) 4pp (quad page program) se * (sector erase) be 32k * (block erase 32kb) 1st byte 06 (hex) 04 (hex) 05 (hex) 01 (hex) 38 (hex) 20 (hex) 52 (hex) 2nd byte val ues ad1 ad1 ad1 3rd byte ad2 ad2 ad2 4th byte ad3 ad3 ad3 action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to read out the values of the status register to write new values of the status register quad input to program the selected page to erase the selected sector to erase the selected 32k block command (byte) be * (block erase 64kb) ce * (chip erase) pp * (page program) dp * (deep power down) rdp * (release from deep power down) pgm/ers suspend * (suspends program/ erase) pgm/ers resume * (resumes program/ erase) 1st byte d8 (hex) 60 or c7 (hex) 02 (hex) b9 (hex) ab (hex) b0 (hex) 30 (hex) 2nd byte ad1 ad1 3rd byte ad2 ad2 4th byte ad3 ad3 action to erase the selected block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode
A25LQ64 series (july, 2014, version 1.4) 14 amic technology corp. security/id/mode setting/reset commands command (byte) rdid (read identification) res (read electronic id) rems (read electronic manufacturer & device id) enso * (enter secured otp) exso * (exit secured otp) rdscur * (read security register) wrscur * (write security register) 1st byte 9f (hex) ab (hex) 90 (hex) b1 (hex) c1 (hex) 2b (hex) 2f (hex) 2nd byte x x 3rd byte x x 4th byte x add (note 2) 5th byte action outputs j e d e c id: 1-byte manufacturer id & 2-byte device id to read out 1-byte device id output the manufacturer id & device id to enter the 4k-bit secured otp mode to exit the 4k- bit secured otp mode to read value of security register to set the lock-down bit as "1" (once lock- down, cannot be update) command (byte) nop * (no operation) rsten * (reset enable) rst * (reset memory) eqio (enable quad i/o ) rstqio (reset quad i/o ) qpiid (qpi id read) sbl * (set burst length) 1st byte 00 (hex) 66 (hex) 99 (hex) 35 (hex) f5 (hex) af (hex) c0 (hex) 2nd byte val ue 3rd byte 4th byte action entering the qpi mode exiting the qpi mode id in qpi interface to set burst length note 1: command set highlighted with (*) are supported both in spi and qpi mode. note 2: the count base is 4-bit for add(2) and dummy(2) because of 2 x i/o. and the msb is on di (io 0 ) which is different from 1 x i/o condition. note 3: add=00h will output the manufacturer id first and add=01h will output device id first. note 4: it is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. note 5: rst command only executed if rsten command is executed first. any intervening command will disable reset.
A25LQ64 series (july, 2014, version 1.4) 15 amic technology corp. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, se, be32k, be, ce, and wrsr, which are intended to change the device content wel bit should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: s goes low sending wren instruction code s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the do[3:1] are don't care in spi mode. (please refer to figure 15-1 and figure 15-2) write disable (wrdi) the write disable (wrdi) instruction is to reset write enable latch (wel) bit. the sequence of issuing wrdi instruction is: s goes low sending wrdi instruction code s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the do[3:1] are don't care in spi mode. (please refer to figure 16-1 and figure 16-2) the wel bit is reset by following situations: - power-up - completion of write disable (wrdi) instruction - completion of write status register (wrsr) instruction - completion of page program (pp) instruction - completion of quad page program (4pp) instruction - completion of sector erase (se) instruction - completion of block erase 32kb (be32k) instruction - completion of block erase (be) instruction - completion of chip erase (ce) instruction - pgm/ers suspend read identification (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the macronix manufacturer id and device id are listed as table 7. id definitions. the sequence of issuing rdid instruction is: s goes low sending rdid instruction code 24-bits id data out on do to end rdid operation can drive s to high at any time during data out. while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. when s goes high, the device is at standby stage. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: s goes low sending rdsr instruction code status register data out on d o. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the do[3:1] are don't care when during spi mode. (please refer to figure 18-1 and figure 18-2) for user to check if program/erase operation is finished or not, rdsr instruction flow are shown as follows:
A25LQ64 series (july, 2014, version 1.4) 16 amic technology corp. program/ erase flow with read array data start wren command rdsr command* wren=1? program/erase command write program data/address (write erase address) rdsr command wip=0? rdsr command read wel=0, bp[3:0], qe, and srwd data read array data (same address of pgm/ers) verify ok? program/erase successfully program/erase another block? program/erase completed program/erase fail no no no yes yes no *issue rdsr to check bp[3:0] yes yes
A25LQ64 series (july, 2014, version 1.4) 17 amic technology corp. program/ erase flow without read array data (read regpfail/regefail flag) start wren command rdsr command* wren=1? program/erase command write program data/address (write erase address) rdsr command wip=0? rdsr command read wel=0, bp[3:0], qe, and srwd data regpfail/ regefail=1? program/erase successfully program/erase another block? program/erase completed program/erase fail no no yes no yes no *issue rdsr to check bp[3:0] yes yes rdscur command
A25LQ64 series (july, 2014, version 1.4) 18 amic technology corp. wrsr flow start wren command rdsr command wren=1? wrsr command write status register data rdsr command wip=0? rdsr command read wel=0, bp[3:0], qe, and srwd data verify ok? wrsr successfully wrsr fail no no no yes yes yes
A25LQ64 series (july, 2014, version 1.4) 19 amic technology corp. the definition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta tus register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is ap plied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/ erase/operations, wip bit needs to be confirm to be 0 before polling wel bit. after wip bit confirmed, wel bit needs to be confirm to be 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defined in table 2) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be ex ecuted. those bits define the protected area of the memory to against page program (pp), sector erase (se), block erase 32kb (be32k), block erase (be) and chip erase (ce) instructions (only if block protect bits (bp3:bp0) set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default. which is unprotected. qe bit. the quad enhance (qe) bit, non-volatile bit, enhances spi quad modes. it controls only hardware protect function in spi mode. it is reset to "0" (factory default) to enable hardware protect function or is set to "1" to disable hardware protect function. t he spi quad i/o commands will be always accepted by flash no matter qe bit is ?1? or ?0?. the qe bit has to be set the through wrsr command status register bit 6. in spi mode and qe bit is ?0?. ( w ) pin should not keep floating in case incidentally hardware protected when srwd bit is ?1?. A25LQ64m-fe fixes qe bit ?1?. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection ( w ) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and w pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. the srwd bit defaults to be "0". status register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (s t a t us register write protect) q e (quad enhance) (note 2) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enhance 0=not quad enhance (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit note 1: see the table 2. protected area size. note 2: A25LQ64m-fe fixes qe bit ?1?.
A25LQ64 series (july, 2014, version 1.4) 20 amic technology corp. write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to define the protected area of memory (as shown in table 2). the wrsr also can set or reset the quad enhance (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection ( w ) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: s goes low sending wrsr instruction code status register data on di s goes high. (please refer to figure 19-1 and figure 19-2) the s must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (t w ) is initiated as soon as chip select ( s ) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the t w timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. A25LQ64m-fe fixes qe bit ?1?, when using this type, the hardware protected mode (hpm) is disabled. table 6. protection modes mode status register condition w and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed w =1 and srwd bit=0, or w =0 and srwd bit=0, or w =1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed w =0, srwd bit=1 the protected area cannot be program or erase. note: 1. as defined by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in table 2. 2. when using A25LQ64m-fe, the hardware protected mode (hpm) is disabled. as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter w is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defined by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and w is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defined by bp3, bp2, bp1, bp0, is at software protected mode (spm). note: if srwd bit=1 but w is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. when using A25LQ64m-fe, the hardware protected mode (hpm) is disabled. hardware protected mode (hpm): - when srwd bit=1, and then w is low (or w is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the w to against data modification. when using A25LQ64m-fe, the hardware protected mode (hpm) is disabled. note: to exit the hardware protected mode requires w driving high once the hardware protected mode is entered. if the w pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. if the system enter qpi or set qe=1, the feature of hpm will be disabled.
A25LQ64 series (july, 2014, version 1.4) 21 amic technology corp. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of serial clock (c), and data shifts out on the falling edge of serial clock (c) at a maximum frequency f r . the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: s goes low sending read instruction code 3-byte address on di data out on do to end read operation can use s to high at any time during data out. (please refer to figure 20) read data bytes at higher speed (fast read) the fast read instruction is for quickly reading data out. the address is latched on rising edge of serial clock (c), and data of each bit shifts out on the falling edge of serial clock (c) at a maximum frequency f c . the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast read instruction. the address counter rolls over to 0 when the highest address has been reached. read on spi mode the sequence of issuing fast read instruction is: s goes low sending fast read instruction code 3-byte address on di 1-dummy byte (default) address on di data out on do to end fast read operation can use s to high at any time during data out. (please refer to figure 21-1) read on qpi mode the sequence of issuing fast read instruction in qpi mode is: s goes low sending fast read instruction, 2 cycles 24-bit address interleave on io 3 , io 2 , io 1 & io 0 4 dummy cycles data out interleave on io 3 , io 2 , io 1 & io 0 to end qpi fast read operation can use s to high at any time during data out. (please refer to figure 21-2) in the performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h,5ah,f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h and afterwards s is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, fast read instruction is rejected without any impact on the program/erase/write status register current cycle. 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of serial clock (c), and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of serial clock (c) at a maximum frequency f t . the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: s goes low sending 2read instruction 24-bit address interleave on io 1 & io 0 4 dummy cycles on io 1 & io 0 data out interleave on io 1 & io 0 to end 2read operation can use s to high at any time during data out (please refer to figure 22. for 2 x i/o read mode timing waveform). while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. the address is latched on rising edge of serial clock (c), and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of serial clock (c) at a maximum frequency f q . the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x i/o read on spi mode (4read) the sequence of issuing 4read instruction is: s goes low sending 4read instruction 24-bit address interleave on io 3 , io 2 , io 1 & io 0 2+4 dummy cycles data out interleave on io 3 , io 2 , io 1 & io 0 to end 4read operation can use s to high at any time during data out. w4read instruction (e7) is also available is spi mode for 4 i/o read. the sequence is similar to 4read, but with only 4 dummy cycles. the clock rate runs at 84mhz. 4 x i/o read on qpi mode (4read) the 4read instruction also support on qpi command mode. the sequence of issuing 4read instruction qpi mode is: s goes low sending 4read instruction 24-bit address interleave io 3 , io 2 , io 1 & io 0 2+4 dummy cycles data out interleave on io 3 , io 2 , io 1 & io 0 to end 4read operation can use s to high at any time during data out (please refer to figure 23. for 4 x i/o read mode timing waveform). another sequence of issuing 4 read instruction especially useful in random access is : s goes low sending 4 read instruction 3-bytes address interleave on io 3 , io 2 , io 1 & io 0 performance enhance toggling bit p[7:0] 4 dummy cycles data out still s goes high s goes low (reduce 4 read instruction) 24-bit random access address (please refer to figure 24-1 and figure 24-2 for 4 x i/o read enhance performance mode timing waveform). in the performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make
A25LQ64 series (july, 2014, version 1.4) 22 amic technology corp. this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh, 00h, aah or 55h and afterwards s is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. burst read this device supports burst read in both spi and qpi mode. to set the burst length, following command operation is required.. issuing command: ?c0h? in the first byte (8-clocks), following 4 clocks defining wrap around enable with ?0h? and disable with?1h?. next 4 clocks is to define wrap around depth. definition as following table: data wrap around wrap depth data wrap around wrap depth 1xh no x 00h yes 8-byte 1xh no x 01h yes 16-byte 1xh no x 02h yes 32-byte 1xh no x 03h yes 64-byte the wrap around unit is defined within the 256byte page, with random initial address. it?s defined as ?wrap-around mode disable? for the default state of the device. to exit wrap around, it is required to issue another ?c0? command in which data=?1xh?. otherwise, wrap around status will be retained until power down or reset command. to change wrap around depth, it is required to issue another ?c0? command in which data=?0xh?. qpi ?0bh? ?ebh? and spi ?ebh? ?e7h? support wrap around feature after wrap around enable. burst read is supported in both spi and qpi mode. the device id default without burst read. spi mode 0123 567 4891011131415 12 s c io[3:0] 10 1 0 0 0 0 0 hhhh l l l l mode 3 mode 0 mode 3 mode 0 qpi mode s c 01 23 io[3:0] c1 c0 h0 l0 msb lsb note: msb = most significant bit lsb = least significant bit mode 3 mode 0 mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 23 amic technology corp. performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. (please note figure 24-1 and figure 24-2. 4 x i/o read e nhance performance mode sequence). performance enhance mode is supported in both spi and qpi mode. in qpi mode, ?ebh? ?0bh? and spi ?ebh? ?e7h? commands support enhance mode. the performance enhance mode is not supported in dual i/o mode. after entering enhance mode, following csb go high, the device will stay in the read mode and treat csb go low of the first clock as address instead of command cycle. to exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. or issue ?ffh? command to exit enhance mode. performance enhance mode reset (ffh) to conduct the performance enhance mode reset operation in spi mode, ffh command code, 8 clocks, should be issued in 1i/o sequence. in qpi mode, ffffffffh command code, 8 clocks, in 4i/o should be issued. (please refer to figure 38) if the system controller is being reset during operation, the flash device will return to the standard spi operation. upon reset of main chip, spi instruction would be issued from the system. instructions like read id (9fh) or fast read (0bh) would be issued. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. (please refer to figure 38) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table of memory organization) is a valid address for sector erase (se) instruction. the s must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits (a22-a12) select the sector address. the sequence of issuing se instruction is: s goes low sending se instruction code 3-byte address on di s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. (please refer to figure 27-1 and figure 27-2) the self-timed sector erase cycle time (t se ) is initiated as soon as chip select ( s ) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the t se timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the sector is protected by bp3, bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the sector. block erase (be32k) the block erase (be32k) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be32k). any address of the block (see table of memory organization) is a valid address for block erase (be32k) instruction. the s must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be32k instruction is: s goes low sending be32k instruction code 3-byte address on di s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. (please refer to figure 28-1 and figure 28-2) the self-timed block erase cycle time (t be 32k) is initiated as soon as chip select ( s ) goes high. the write in progress (wip) bit still can be check out during the block erase cycle is in progress. the wip sets 1 during the t be 32k timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (t be 32k) instruction will not be executed on the block. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (please refer to table of memory organization) is a valid address for block erase (be) instruction. the s must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: s goes low sending be instruction code 3-byte address on di s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. (please refer to figure 29-1 and figure 29-2) the self-timed block erase cycle time (t se ) is initiated as soon as chip select ( s ) goes high. the write in progress (wip) bit still can be check out during the block erase cycle is in progress. the wip sets 1 during the t se timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the block. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the s must go high exactly at the byte boundary, otherwise th e instruction will be rejected and not executed. the sequence of issuing ce instruction is: s goes low sending ce instruction code s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can
A25LQ64 series (july, 2014, version 1.4) 24 amic technology corp. accept by this instruction. the io[3:1] are don't care when during spi mode. (please refer to figure 30-1 and figure 30-2) the self-timed chip erase cycle time (t ce ) is initiated as soon as chip select ( s ) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the t ce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3, bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3, bp2, bp1, bp0 all set to "0". page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. if the entire 256 data bytes are going to be programmed, a7-a0 (the eight least significant address bits) should be set to 0. if the eight least significant address bits (a7-a0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address a7-a0 are all 0). if more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. the sequence of issuing pp instruction is: s goes low sending pp instruction code 3-byte address on di at least 1-byte on data on di s goes high. (please refer to figure 25-1 and figure 25-2) the s must be kept to low during the whole page program cycle; the s must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (t pp ) is initiated as soon as chip select ( s ) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the t pp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the quad page program (4pp). the quad page programming takes four pins: io 0 , io 1 , io 2 , and io 3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33mhz. for system with faster clock, the quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: s goes low sending 4pp instruction code 3-byte address on io[3:0] at least 1-byte on data on io[3:0] s goes high. deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to entering the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when s goes high, it's only in deep power-down mode not standby mode. it's different from standby mode. the sequence of issuing dp instruction is: s goes low sending dp instruction code s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. (please refer to figure 31-1 and figure 31-2) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction and softreset command. (those instructions allow the id being reading out). when power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for dp instruction the s must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select ( s ) goes high, a delay of t dp is required before entering the deep power-down mode. release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select ( s ) high. when chip select ( s ) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select ( s ) must remain high for at least tres2(max), as specified in table 12. ac characteristics. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id definitions on next page. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. the sequence is shown as figure 32, figure 33-1 and figure 33-2. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. only spi (8 clocks) command cycle can accept by this instruction.
A25LQ64 series (july, 2014, version 1.4) 25 amic technology corp. the res instruction is ended by s goes high after the id been read out at least once. the id outputs repeatedly if continuously send the additional clock cycles on serial clock (c) while s is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of t res2 to transit to standby mode, and s must remain to high at least t res2 (max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the s pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id (37h) and the device id are shifted out on the falling edge of serial clock (c) with most significant bit (msb) first as shown in figure 34 the device id values are listed in table 7 of id definitions. if the one-byte address is initially set to 01h, then the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving s high. qpi id read (qpiid) the qpiid is quad mode rdid A25LQ64. the sequence of issue qpiid instruction is s goes low sending qpi id instruction data out on do s goes high. most significant bit (msb) first. immediately following the command cycle the device outputs data on the falling edge of the serial clock (c) signal. the data output stream is continuous until terminated by a low to high transition of s . the device outputs three bytes of data: manufacturer, device type, and device id. table 7. id definitions command type A25LQ64 manufacturer id memory type memory density rdid (jedec id) 37 40 17 electronic id res 17 manufacturer id device id rems 37 16 enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. the additional 4k-bit secured otp is independent from main array, which may use to store unique serial number for system identifier. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: s goes low sending enso instruction to enter secured otp mode s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: s goes low sending exso instruction to exit secured otp mode s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : s goes low sending rdscur instruction security register data out on do s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. the definition of the security register bits is as below: lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for customer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be update any more. while it is in 4k-bit secured otp mode, main array access is not allowed. write security register (wrscur) the wrscur instruction is for setting the values of security register bits. the wren (write enable) instruction is required before issuing wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the ldso bit is an otp bit. once the ldso bit is set, the value of ldso bit can not be altered any more. the sequence of issuing wrscur instruction is : s goes low sending wrscur instruction status register data on di s goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. the s must go high exactly at the boundary; otherwise, the instruction will be reje cted and not executed.
A25LQ64 series (july, 2014, version 1.4) 26 amic technology corp. table 8. security register definition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e_fail p_fail reserved erase suspend bit program suspend bit ldso (indicate if lock-down) reserved 0 0=normal erase succeed 1=individual erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) - 0=erase is not suspended 1= erase suspended (default=0) 0=program is not suspended 1= program suspended (default=0) 0 = not lock- down 1 = lock-down (cannot program/ erase otp ) 0 read only volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit (otp) read only read unique id number (4bh) (1) the read unique id number instruction accesses a factory-set read-only 64-byte number that is unique to each A25LQ64 device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the read unique id instruction is initiated by driving the s pin low and shifting the instruction code ?4bh? followed by a four bytes of dummy clocks. after which, the 64- byte id is shifted out on the falling edge of serial clock (c) as shown in figure 7. figure 7. read unique id number instruction sequence instruction (4bh) high impedance 810 9 01234 5 6 7 dummy byte 1~3 28 29 30 31 23 22 21 3 210 data out 1 data out 2 7 0 s c di do s c di do 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte 4 msb 0 msb msb 32 mode 3 mode 0 7 6 54 32 1 6 54 1 0 7 64-byte (512-bit) unique serial number note: for A25LQ64 this feature is available upon special request. please contact amic for details.
A25LQ64 series (july, 2014, version 1.4) 27 amic technology corp. read sfdp mode (5ah) read sfdp mode A25LQ64 features serial flash discoverable parameters (sfdp) mode. host system can retrieve the operating characteristics, structure and vendor specified information such as identifying information, memory size, operating voltage and timing information of this device by sfdp mode. the device is first selected by driving chip select ( s ) low. the instruction code for the read sfdp mode is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on do, each bit being shifted out, at a maximum frequency fr, during the falling edge of serial clock (c). the instruction sequence is shown in figure 8. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single serial flash discoverable parameters (sfdp) instruction. when the highest address is reached, the address counter rolls over to 0x00h, allowing the read sequence to be continued indefinitely. the serial flash discoverable parameters (sfdp) instruction is terminated by driving chip select ( s ) high. chip select ( s ) can be driven high at any time during data output. any read data bytes at serial flash discoverable parameters (sfdp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 8. read sfdp mode instruction sequence diagram instruction (5ah) high impedance 810 9 012345 6 7 24-bit address 28 29 30 31 23 22 21 3 210 data out 1 data out 2 7 0 s c di do s c di do 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte msb 0 msb msb 32 mode 3 mode 0 7 6 54 32 1 6 54 1 0 7 note: please note the above address cycles are base on 3-byte address mode.
A25LQ64 series (july, 2014, version 1.4) 28 amic technology corp. table 9. serial flash discoverable parameters (sfdp) signature and parameter identification data value (advanced information) description address (h) (byte mode) data (bit) data comment 00h 07 : 00 53h 01h 15 : 08 46h 02h 23 : 16 44h sfdp signature 03h 31 : 24 50h signature [31:0]: hex: 50444653 sfdp minor revision number 04h 07 : 00 00h star from 0x00 sfdp major revision number 05h 15 : 08 01h star from 0x01 number of parameter headers (nph) 06h 23 : 16 00h 1 parameter header unused 07h 31 : 24 ffh reserved id number 08h 07 : 00 00h parameter table minor revision number 09h 15 : 08 00h star from 0x00 parameter table major revision number 0ah 23 : 16 01h star from 0x01 parameter table length (in dw) 0bh 31 : 24 09h 9 dwords 0ch 07 : 00 30h 0dh 15 : 08 00h parameter table pointer (ptp) 0eh 23 : 16 00h 000030h unused 0fh 31 : 24 ffh reserved
A25LQ64 series (july, 2014, version 1.4) 29 amic technology corp. table 10. parameter id (0) (advanced information) description address (h) (byte mode) data (bit) data comment 00 block / sector erase sizes identifies the erase granularity for all flash components 01 01b 00 = reserved 01 = 4kb erase 10 = reserved 11 = 64kb erase write granularity 02 1b 0 = no, 1 = yes write enable instruction required for writing to volatile status register 03 write enable opcode select for writing to volatile status register 04 00b 00 = n/a 01 = use 50h opcode 11 = use 06h opcode 05 06 unused 30h 07 111b reserved 08 09 10 11 12 13 14 4 kilo-byte erase opcode 31h 15 20h 4 kb erase support (ffh = not supported) supports (1-1-2) fast read device supports single input opcode & address and dual output data fast read 16 1b 0 = not supported 1 = supported 17 address byte number of bytes used in addressing for flash array write and erase. 18 00b 00 = 3-byte 01 = 3- or 4-byte (e.g. defaults to 3-byte mode; enters 4-byte mode on command) 10 = 4-byte 11 = reserved supports double transfer rate (dtr) clocking indicates the device supports some type of double transfer rate clocking. 19 0b 0 = not supported 1 = supported supports (1-2-2) fast read device supports single input opcode, dual input address, and dual output data fast read 20 1b 0 = not supported 1 = supported supports (1-4-4) fast read device supports single input opcode, quad input address, and quad output data fast read 21 1b 0 = not supported 1 = supported supports (1-1-4) fast read device supports single input opcode & address and quad output data fast read 22 0b 0 = not supported 1 = supported unused 32h 23 1b reserved 24 25 26 27 28 29 30 unused 33h 31 ffh reserved
A25LQ64 series (july, 2014, version 1.4) 30 amic technology corp. table 10. parameter id (0) (advanced information) (continued) description address (h) (byte mode) data (bit) data comment flash memory density 37h : 34h 31 : 00 03ffffffh 64 mbits table 10. parameter id (0) (advanced information) (continued) description address (h) (byte mode) data (bit) data comment 00 01 02 03 (1-4-4) fast read number of wait states (dummy clocks) needed before valid output 04 00100b 4 dummy clocks 05 06 quad input address quad output (1-4- 4) fast read number of mode bits 38h 07 010b 8 mode bits 08 09 10 11 12 13 14 (1-4-4) fast read opcode opcode for single input opcode, quad input address, and quad output data fast read. 39h 15 ebh 16 17 18 19 (1-1-4) fast read number of wait states (dummy clocks) needed before valid output 20 00000b not supported 21 22 (1-1-4) fast read number of mode bits 3ah 23 000b not supported (1-1-4) fast read opcode opcode for single input opcode & address and quad output data fast read. 3bh 31 : 24 ffh not supported
A25LQ64 series (july, 2014, version 1.4) 31 amic technology corp. table 10. parameter id (0) (advanced information) (continued) description address (h) (byte mode) data (bit) data comment 00 01 02 03 (1-1-2) fast read number of wait states (dummy clocks) needed before valid output 04 01000b 8 dummy clocks 05 06 (1-1-2) fast read number of mode bits 3ch 07 000b not supported (1-1-2) fast read opcode opcode for single input opcode & address and dual output data fast read. 3dh 15 : 08 3bh 16 17 18 19 (1-2-2) fast read number of wait states (dummy clocks) needed before valid output 20 00100b 4 dummy clocks 21 22 (1-2-2) fast read number of mode bits 3eh 23 000b not supported (1-2-2) fast read opcode opcode for single input opcode, dual input address, and dual output data fast read. 3fh 31 : 24 bbh table 10. parameter id (0) (advanced information) (continued) description address (h) (byte mode) data (bit) data comment supports (4-4-4) fast read device supports quad input opcode & address and quad output data fast read. 00 1b 0 = not supported 1 = supported 01 02 reserved. these bits default to all 1?s 03 111b reserved supports (2-2-2) fast read device supports dual input opcode & address and dual output data fast read. 04 0b 0 = not supported 1 = supported 05 06 reserved. these bits default to all 1?s 40h 07 111b reserved reserved. these bits default to all 1?s 43h : 41h 31 : 08 ffh reserved
A25LQ64 series (july, 2014, version 1.4) 32 amic technology corp. table 10. parameter id (0) (advanced information) (continued) description address (h) (byte mode) address (bit) data comment reserved. these bits default to all 1?s 45h : 44h 15 : 00 ffh reserved 16 17 18 19 (2-2-2) fast read number of wait states (dummy clocks) needed before valid output 20 00000b not supported 21 22 (2-2-2) fast read number of mode bits 46h 23 000b not supported (2-2-2) fast read opcode opcode for dual input opcode & address and dual output data fast read. 47h 31 : 24 ffh not supported table 10. parameter id (0) (advanced information) (continued) description address (h) (byte mode) address (bit) data comment reserved. these bits default to all 1?s 49h : 48h 15 : 00 ffh reserved 16 17 18 19 (4-4-4) fast read number of wait states (dummy clocks) needed before valid output 20 00100b 4 dummy clocks 21 22 (4-4-4) fast read number of mode bits 4ah 23 010b 8 mode bits (4-4-4) fast read opcode opcode for quad input opcode/address, quad output data fast read. 4bh 31 : 24 ebh must enter qpi mode firstly table 10. parameter id (0) (advanced information) (continued) description address (h) (byte mode) address (bit) data comment sector type 1 size 4ch 07 : 00 0ch 4 kb sector type 1 opcode 4dh 15 : 08 20h sector type 2 size 4eh 23 : 16 0fh 32 kb sector type 2 opcode 4fh 31 : 24 52h table 10. parameter id (0) (advanced information) (continued) description address (h) (byte mode) address (bit) data comment sector type 3 size 50h 07 : 00 10h 64 kb sector type 3 opcode 51h 15 : 08 d8h sector type 4 size 52h 23 : 16 00h not supported sector type 4 opcode 53h 31 : 24 ffh not supported
A25LQ64 series (july, 2014, version 1.4) 33 amic technology corp. program/erase suspend/resume the device allow the interruption of sector-erase, block-erase or page-program operations and conduct other operations. details as follows. to enter the suspend/resume mode: issuing b0h for suspend; 30h for resume (spi/qpi all acceptable) read security register bit2 (psb) and bit3 (esb) (please refer to table 11 to check suspend ready information. suspend to suspend ready timing: 20 s. resume to another suspend timing: 1ms. esb bit (erase suspend bit) indicates the status of erase suspend operation. when issue a suspend command during erase operation esb=1, when erase operation resumes, esb will be reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. erase suspend erase suspend allow the interruption of all erase operations. after erase suspend, wel bit will be clear, only read related, resume and reset command can be accepted unconditionally. (including: 03h, 0bh, 3bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 3ch, 30h, 66h, 99h, c0h, 35h, f5h, 00h, abh) for erase suspend to program operation, the programming command (38, 02) can be accepted under conditions as follows: the block group (bg) is divided into 32bgs in this device, each bg's density is 2mb. while conducting erase suspend in one bg, the programming operation that follows can only be conducted in one of the other bgs and should not be conducted in the bg executing the suspend operation. the boundaries of the bgs are illustrated as below table. bg (2m bit) address range bg (2m bit) address range 31 7c0000h-7fffffh 15 3c0000h-3fffffh 30 780000h-7bffffh 14 380000h-3bffffh 29 740000h-77ffffh 13 340000h-37ffffh 28 700000h-73ffffh 12 300000h-33ffffh 27 6c0000h-6fffffh 11 2c0000h-2fffffh 26 680000h-6bffffh 10 280000h-2bffffh 25 640000h-67ffffh 9 240000h-27ffffh 24 600000h-63ffffh 8 200000h-23ffffh 23 5c0000h-5fffffh 7 1c0000h-1fffffh 22 580000h-5bffffh 6 180000h-1bffffh 21 540000h-57ffffh 5 140000h-17ffffh 20 500000h-53ffffh 4 100000h-13ffffh 19 4c0000h-4fffffh 3 0c0000h-0fffffh 18 480000h-4bffffh 2 080000h-0bffffh 17 440000h-47ffffh 1 040000h-07ffffh 16 400000h-43ffffh 0 000000h-03ffffh after issue erase suspend command, latency time 20 s is needed before issue another command. for "suspend to read", "resume to read", "resume to suspend" timing specification please note figure 41-1, figure 41-2 and figure 41-3. esb bit (erase suspend bit) indicates the status of erase suspend operation. when issue a suspend command during program operation esb=1, when erase operation resumes, esb will be reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. when esb bit is issued, the write enable latch (wel) bit will be reset. see figure 41-1 for suspend to read latency.
A25LQ64 series (july, 2014, version 1.4) 34 amic technology corp. program suspend program suspend allows the interruption of all program operations. after program suspend, wel bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0bh, 3bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 3ch, 30h, 66h, 99h, c0h, 35h, f5h, 00h, abh) after issue program suspend command, latency time 20 s is needed before issue another command. for "suspend to read", "resume to read", "resume to suspend" timing specification please note figure 41-1, figure 41-2 and figure 41-3. psb bit (program suspend bit) indicates the status of program suspend operation. when issue a suspend command during program operation psb=1, when program operation resumes, psb will be reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. write-resume the write operation is being resumed when write-resume instruction issued. esb or psb (suspend status bit) in status register will be changed back to ?0? the operation of write-resume is as follows: s drives low send write resume command cycle (30h) drive s high. by polling busy bit in status register, the internal write operation status could be checked to be completed or not. the user may also wait the time lag of tse, tbe, tpp for sector-erase, block-erase or page-programming. wren (command "06" is not required to issue before resume. resume to another suspend operation requires latency time of 1ms. please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resume. to restart the write command, disable the "performance enhance mode" is required. after the "performance enhance mode" is disable, the write-resume command is effective. no operation (nop) the no operation command only cancels a reset enable command. nop has no impact on any other command. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. software reset (reset-enable (rsten) and reset (rst)) the reset operation is used as a system (software) reset that puts the device in normal operating ready mode. this operation consists of two commands: reset-enable (rsten) and reset (rst). to reset the A25LQ64 the host drives s low, sends the reset-enable command (66h), and drives s high. next, the host drives s low again, sends the reset command (99h), and drives s high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. the reset operation requires the reset-enable command followed by the reset command. any command other than the reset command after the reset-enable command will disable the reset-enable. a successful command execution will reset the device to spi stand-by read mode, which are their respective default states, see figure 42. a device reset during an active program or erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. depending on the prior operation, the reset timing may vary. recovery from a write operation requires more latency time than recovery from other operations. reset quad i/o (rstqio) the reset quad i/o instruction, f5h, resets the device to 1-bit spi protocol operation. to execute a reset quad i/o operation, the host drives s low, sends the reset quad i/o command cycle (f5h) then, drives s high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the io[3:1] are don't care when during spi mode. note: for eqio/rstqio/c0 pcsb high width has to follow "write spec" t shsl as 30ns for next instruction. power-on state the device is at below states when power-up: - standby mode (please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the v cc achieves below correct level: - v cc minimum at power-up stage and then after a delay of t vsl - v ss at power-down please note that a pull-up resistor on s may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. during power on, when v cc is lower than v wi (por threshold voltage value), the internal logic is reset and the flash device has no response to any command. for further protection on the device, after v cc reaching the v wi level, a t puw time delay is required before the device is fully accessible for commands like write enable (wren), page program (pp), quad page program (4pp), sector erase (se), block erase 32kb (be32k), block erase (be), chip erase (ce), wrscur and write status register (wrsr). if the v cc does not reach the v cc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - t puw after v cc reached v wi level - t vsl after v cc reached v cc minimum level the device can accept read command after v cc reached v cc minimum and a time delay of t vsl , even time of t puw has not passed. please refer to the figure of "power-up timing". note: - to stabilize the v cc level, the v cc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1 f) - at power-down stage, the v cc drops below v wi level, all operations are disable and device has no response to any write command. the data corruption might occur during the stage while a write, program, erase cycle is in progress.
A25LQ64 series (july, 2014, version 1.4) 35 amic technology corp. electrical specifications absolute maximum ratings rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to v cc +4.6v applied output voltage -0.5v to v cc +4.6v v cc to ground potential -0.5v to v cc +4.6v notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum ratin g conditions for extended period may affect reliability. 2. specifications contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to v ss to -2.0v and v cc to +2.0v for period up to 20ns. figure 9. maximum negative input overshoot 20ns v ss v ss - 2.0v figure 10. maximum positive input overshoot 20ns v cc v cc + 2.0v capacitance (t a = 25 c, f = 1.0mhz) symbol parameter test condition min. max. unit c out output capacitance (do) v out = 0v 6 pf c in input capacitance (other pins) v in = 0v 8 pf
A25LQ64 series (july, 2014, version 1.4) 36 amic technology corp. figure 11. ac measurement i/o waveform 0.3v cc 0.5v cc 0.2v cc 0.7v cc 0.8v cc input levels input and output timing reference levels
A25LQ64 series (july, 2014, version 1.4) 37 amic technology corp. table 11. dc characteristics (t a = -40c to 85c, v cc = 2.7v ~ 3.6v) symbol parameter notes min. typ. max. units test conditions i li input load current 1 2 a v cc = v cc max, v in = v cc or v ss i lo output leakage current 1 2 a v cc = v cc max, v out = v cc or v ss i sb1 v cc standby current 1 2 10 a v in = v cc or v ss , s = v cc i sb2 deep power-down current 2 10 a v in = v cc or v ss , s = v cc 15 25 ma f=104mhz, (4 x i/o read) c=0.1 v cc /0.9 v cc , do=open 10 15 ma f=104mhz, (1 x i/o read) c=0.1 v cc /0.9 v cc , do=open 14 20 ma f q =84mhz, (4 x i/o read) c=0.1 v cc /0.9 v cc , do=open 10 15 ma f t =84mhz, (2 x i/o read) c=0.1 v cc /0.9 v cc , do=open i cc1 v cc read 1 6 8 ma f =33mhz, c=0.1 v cc /0.9 v cc , do=open i cc2 v cc program current (pp) 1 20 25 ma program in progress, s = v cc i cc3 v cc write status register (wrsr) current 20 ma program status register in progress, s = v cc i cc4 v cc sector/block (32k, 64k) erase current (se/be/be32k) 1 20 25 ma erase in progress, s = v cc i cc5 v cc chip erase current (ce) 1 20 25 ma erase in progress, s = v cc v il input low voltage -0.5 0.8 v v ih input high voltage 0.7 v cc v cc +0.4 v v ol output low voltage 0.4 v i ol = 1.6ma v oh output high voltage v cc -0.2 v i oh = -100 a notes: 1. typical values at v cc = 3.3v, t a = 25c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation.
A25LQ64 series (july, 2014, version 1.4) 38 amic technology corp. table 12. ac characteristics (t a = -40c to 85c, v cc = 2.6v ~ 3.7v) symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast read, pp, 4pp, se, be, ce, dp, res, rdp wren, wrdi, rdid, rdsr, wrsr d.c. 104 mhz f rc f r clock frequency for read instructions 66 mhz f t clock frequency for 2read instructions 84 mhz f tc f q clock frequency for 4read instructions (5) 84/104 mhz serial (f c ) 4.5 ns t ch (1)(2) t clh clock high time 4pp and normal read (f rc ) 4.5 ns serial (f c ) 4.5 ns t cl (1)(2) t cll clock low time 4pp and normal read (f rc ) 4.5 ns t clch (2) clock rise time (3) (peak to peak) 0.1 v/ns t chcl (2) clock fall time (3) (peak to peak) 0.1 v/ns t slch (2) t css s active setup time (relative to c) 4 ns t chsl (2) s not active hold time (relative to c) 4 ns t dvch t dsu data in setup time 2 ns t chdx (2) t dh data in hold time 3 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns read 10 ns t shsl (3) t csh s deselect time write/erase/program 30 ns t shqz (2) t dis output disable time 8 ns loading: 30pf 8 ns t clqv t v clock low to output valid loading: 30pf/15pf loading: 15pf 6 ns t clqx t ho output hold time 0 ns t whsl write protect setup time 20 ns t shwl write protect hold time 100 ns t dp (2) s high to deep power-down mode 10 s t res1 (2) s high to standby mode without electronic signature read 10 s t res2 (2) s high to standby mode with electronic signature read 10 s t rcr recovery time from read 20 s t rcp recovery time from program 20 s t rce recovery time from erase 12 ms t w write status register cycle time 40 ms t bp byte-program 6 30 s t pp page program cycle time 0.3 0.8/2 (6) ms t se sector erase cycle time 40 150 ms t be32 block erase (32kb) cycle time 80 300 ms t be block erase (64kb) cycle time 120 500 ms t ce chip erase cycle time 12 25 s notes: 1. t ch + t cl must be greater than or equal to 1/ frequency. 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 4. test condition is shown as figure 11. 5. when dummy cycle=4 (in both qpi & spi mode), clock rate=84mhz; when dummy cycle=6 (in both qpi & spi mode), clock rate=104mhz. 6. the page program time is 0.8ms(max.) after 10k cycling and 2ms(max.) after 100k cycling.
A25LQ64 series (july, 2014, version 1.4) 39 amic technology corp. timing analysis figure 12. serial input timing s c di t shsl high impedance do t slch t chsl t shch t chdx t chsh t dvch t clch lsb in msb in t chcl figure 13. output timing s c do di addr.lsb in lsb t clqv t clqv t ch t clqx t clqx t cl t shqz
A25LQ64 series (july, 2014, version 1.4) 40 amic technology corp. figure 14. write protect setup and hold timing during wrsr when srwd=1 high impedance t whsl t shwl s c di do w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01h figure 15-1. write enable (wren) sequence (command 06) (spi mode) s c di do high impedance command 01234567 06h mode 3 mode 0 figure 15-2. write enable (wren) sequence (command 06) (qpi mode) s c 01 io[3:0] 06h command mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 41 amic technology corp. figure 16-1. write disable (wrdi) sequence (command 04) (spi mode) s c di do high impedance command 04h 01 23 45 6 7 mode 3 mode 0 figure 16-2. write disable (wrdi) sequence (command 04) (qpi mode) s c 01 io[3:0] 04h command mode 3 mode 0 figure 17. read identification (rdid) sequence (command 9f) (spi mode only) s c di do command high impedance manufacture id 0 765 321 9fh 810 9 01234567 11 13 12 14 15 16 28 29 30 31 17 18 15 14 13 2 1 3 0 device id msb msb mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 42 amic technology corp. figure 18-1. read status register (rdsr) sequence (command 05) (spi mode) 0 1 2 3 4 5 6 7 810 91112 13 14 15 msb msb status register out status register out high impedance command 01234567 0 1 2 3 4 5 6 77 s di do c 05h mode 3 mode 0 figure 18-2. read status register (rdsr) sequence (command 05) (qpi mode) s c status byte 05h 8 01 2 3 4 56 7 msb io[3:0] n h0 l0 h0 l0 h0 l0 h1 l1 lsb status byte status byte status byte mode 3 mode 0 figure 19-1. write status register (wrsr) sequence (command 01) (spi mode) 810 91112 13 14 15 msb status register in high impedance command 01234 5 6 7 s di do c 01h 76543210 note: also supported in qpi mode with command and subsequent input/output in quad i/o mode. mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 43 amic technology corp. figure 19-2. write status register (wrsr) sequence (command 01) (qpi mode) status register in command s c io 0 c4, c0 0 4 io 1 c5, c1 1 5 io 2 c6, c2 2 6 io 3 c7, c3 3 7 mode 3 mode 0 figure 20. read data bytes (read) sequence (command 03) (spi mode only) (33mhz) di do command high impedance 23 22 21 3 2 1 810 9 0 1 2 3 4 5 6 7 28 29 30 31 7 s c 32 33 34 35 36 37 38 39 msb 03h 0 76543 210 data out 1 data out 2 24-bit address mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 44 amic technology corp. figure 21-1. read at higher speed (fast read) sequence (command 0b) (spi mode) (104mhz) command high impedance 810 9 012345 6 7 24-bit address 28 29 30 31 23 22 21 3 210 data out 1 data out 2 7 0 s c di do s c di do 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte msb 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0 0bh mode 3 mode 0 figure 21-2. read at higher speed (fast read) sequence (command 0b) (qpi mode) (84mhz) 810 91112 13 14 15 24-bit address command 012345 6 7 s c 0bh xxxxh0l0h1l1 io[3:0] a5 a4 a3 a2 a1 a0 data in msb lsb data out 1 msb lsb data out 2 mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 45 amic technology corp. figure 22. 2 x i/o read mode sequence (command bb) (spi mode only) (84mhz) s c di 8 - bit instruction high impedance bbh 810 9 01234567 11 19 18 20 21 22 25 26 27 23 24 address bit22, bit20, bit18 bit0 data bit6, bit4, bit2 bit0, bit6, bit4 address bit23, bit21, bit19 bit1 data bit7, bit5, bit3 bit1, bit7, bit5 12-bit address 4 dummy cycle data output do mode 3 mode 0 figure 23. 4 x i/o read mode sequence (command eb) (spi mode) (104mhz) s c io 0 8-bit instruction high impedance ebh 810 9 01234567 11 13 12 14 15 16 19 20 21 17 18 address bit20, bit16, bit0 data bit4, bit0, bit4 6 address cycles 4 dummy cycle data output io 1 22 23 n p4 p0 p5 p1 performance enhance indicator (note) io 2 p6 p2 io 3 p7 p3 address bit21, bit17, bit1 address bit22, bit18, bit2 address bit23, bit19, bit3 data bit5, bit1, bit5 data bit6, bit2, bit6 data bit7, bit3, bit7 high impedance high impedance mode 3 mode 0 notes: 1. also supported in qpi mode with command and subsequent input/output in quad i/o mode and runs at 104mhz. 2. hi-impedance is inhibited for the two clock cycles. 3. p7 p3, p6 p2, p5 p1 & p4 p0 (toggling) is inhibited.
A25LQ64 series (july, 2014, version 1.4) 46 amic technology corp. figure 24-1. 4 x i/o read enhance performance mode sequence (command eb) (spi mode) (104mhz) s c io 0 8-bit instruction high impedance ebh 810 9 01234567 11 13 12 14 15 16 19 20 21 17 18 address bit20, bit16, bit0 data bit4, bit0, bit4 6 address cycles 4 dummy cycle data output io 1 22 23 n p4 p0 p5 p1 performance enhance indicator (note) io 2 p6 p2 io 3 p7 p3 address bit21, bit17, bit1 address bit22, bit18, bit2 address bit23, bit19, bit3 data bit5, bit1, bit5 data bit6, bit2, bit6 data bit7, bit3, bit7 high impedance high impedance s c 6 address cycles n+9 n+1 n+7 n+13 data bit4, bit0, bit4 4 dummy cycle data output p4 p0 p5 p1 performance enhance indicator (note) p6 p2 p7 p3 data bit5, bit1, bit5 data bit6, bit2, bit6 data bit7, bit3, bit7 address bit20, bit16, bit0 address bit21, bit17, bit1 address bit22, bit18, bit2 address bit23, bit19, bit3 mode 3 mode 0 io 0 io 1 io 2 io 3 notes: performance enhance mode, if p7 p3 & p6 p2 & p5 p1 & p4 p0 (toggling), ex: a5, 5a, 0f, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff
A25LQ64 series (july, 2014, version 1.4) 47 amic technology corp. figure 24-2. 4 x i/o read enhance performance mode sequence (command eb) (qpi mode) (104mhz) figure 25-1. page program (pp) sequence (command 02) (spi mode) s c di command msb 810 9 012345 6 7 24-bit address 28 29 30 31 32 33 34 35 36 37 38 39 23 22 21 3 210 data byte 1 msb 7 6 54 32 1 0 3 data byte 256 55 53 54 52 data byte 3 51 50 49 48 47 46 45 44 43 42 41 40 data byte 2 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0 msb 7 6 54 32 1 0 s c di 2072 2073 2074 2075 2076 2077 2078 2079 02h mode 3 mode 0 data in io[3:0] 0123 567 4891011131415 12 s c ebh a5a4a3a2a1a0 x x h0l0h1l1 msb 16 17 x x p(7:4)p(3:0) performance enhance indicator 4 dummy cycle data out lsb msb lsb 6 address cycles io[3:0] n+1 s c a5 a4 a3 a2 a1 a0 x x msb x x p(7:4) p(3:0) performance enhance indicator 4 dummy cycle data out lsb msb lsb h0 l0 h1 l1 mode 3 mode 0 mode 0
A25LQ64 series (july, 2014, version 1.4) 48 amic technology corp. figure 25-2. page program (pp) sequence (command 02) (qpi mode) command 012 s c 02h h0 l0 h1 l1 io[3:0] a5 a4 a3 a2 a1 a0 data in data byte 1 h2 l2 h3 l3 h255 l255 data byte 2 data byte 3 data byte 4 data byte 256 24-bit address mode 3 mode 0 figure 26. 4 x i/o page program (4pp) sequence (command 38) (spi mode only) data byte 4 data byte 3 data byte 2 data byte 1 io 0 0123 567 4891011131415 12 s c 38h 2016128 40 4040 16 17 4 0 18 19 20 21 command 6 address cycle 40 2117139 51 5151 51 51 22181410 62 6262 6 2 62 23191511 73 7373 7 3 73 io 1 io 2 io 3 mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 49 amic technology corp. figure 27-1. sector erase (se) sequence (command 20) (spi mode) command msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 s c di 22 21 3 210 0 23 20h mode 3 mode 0 figure 27-2. sector erase (se) sequence (command 20) (qpi mode) command msb 24-bit address 23 s c a4 a3 a2 a1 a0 a5 20h io[3:0] 01 23 5 6 7 4 lsb mode 3 mode 0 figure 28-1. block erase 32kb (be32k) sequence (command 52) (spi mode) command msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 s c di 22 21 3 210 0 23 52h mode 3 mode 0 figure 28-2. block erase 32kb (be32k) sequence (command 52) (qpi mode) command msb 24-bit address 23 s c a4 a3 a2 a1 a0 a5 52h io[3:0] 01 23 5 6 7 4 mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 50 amic technology corp. figure 29-1. block erase (be) sequence (command d8) (spi mode) command msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 s c di 22 21 3 210 0 23 d8h mode 3 mode 0 figure 29-2. block erase (be) sequence (command d8) (qpi mode) command msb 24-bit address 23 s c a4 a3 a2 a1 a0 a5 d8h io[3:0] 01 23 5 6 7 4 mode 3 mode 0 figure 30-1. chip erase (ce) sequence (command 60 or c7) (spi mode) command s c 60h or c7h di 01 23 5 6 7 4 mode 3 mode 0 figure 30-2. chip erase (ce) sequence (command 60 or c7) (qpi mode) command s c 60h or c7h io[3:0] 01 mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 51 amic technology corp. figure 31-1. deep power-down (dp) sequence (command b9) (spi mode) s c di 1 2 3 4567 0 command t dp stand-by mode deep power-down mode b9h mode 3 mode 0 figure 31-2. deep power-down (dp) sequence (command b9) (qpi mode) s t dp stand-by mode deep power-down mode b9h command c 01 io[3:0] mode 3 mode 0 figure 32. release from deep power-down and read electronic signature (res) sequence (command ab) (spi mode only) s c di do command high impedance msb msb 810 9 012345 6 7 3 dummy bytes 28 29 30 31 32 33 34 35 36 37 38 23 22 21 3 210 6 54 32 10 7 t res2 stand-by mode deep power-down mode abh electronic signature out mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 52 amic technology corp. figure 33-1. release from deep power-down (rdp) sequence (command ab) (spi mode) stand-by mode deep power-down mode s c di 1 2 3 4567 0 command t res1 abh do high impedance mode 3 mode 0 figure 33-2. release from deep power-down (rdp) sequence (command ab) (qpi mode) s t res1 stand-by mode deep power-down mode abh command c 01 io[3:0] mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 53 amic technology corp. figure 34. read electronic manufacturer & device id (rems) sequence (command 90) (spi mode only) command high impedance msb 810 9 01 234 5 6 7 2 dummy bytes 20 21 22 23 15 14 13 3 210 manufacturer id 0 s c di do s c di do 24 25 26 27 28 29 30 31 654 1 7 3 32 33 34 35 36 37 38 39 20 add (1) msb 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0 40 41 42 43 44 45 46 47 device id 90h 7 mode 3 mode 0 notes: 1. add=00h will output the manufacturer's id first and add=01h will output device id first.
A25LQ64 series (july, 2014, version 1.4) 54 amic technology corp. figure 35-1. read security register (rdscur) sequence (command 2b) (spi mode) 0 1 2 3 4 5 6 7 810 91112 13 14 15 msb msb status register out status register out high impedance command 01234567 0 1 2 3 4 5 6 77 s di do c 2b mode 3 mode 0 figure 35-2. read security register (rdscur) sequence (command 2b) (qpi mode) s c status byte 2b 8 01 2 3 4 56 7 msb io[3:0] n h0 l0 h0 l0 h0 l0 h1 l1 lsb status byte status byte status byte mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 55 amic technology corp. figure 36-1. write security register (wrscur) sequence (command 2f) (spi mode) 810 91112 13 14 15 msb status register in high impedance command 01234 5 6 7 s di do c 2fh 76543210 note: also supported in qpi mode with command and subsequent input/output in quad i/o mode. mode 3 mode 0 figure 36-2. write security register (wrscur) sequence (command 2f) (qpi mode) status register in command s c io 0 c4, c0 0 4 io 1 c5, c1 1 5 io 2 c6, c2 2 6 io 3 c7, c3 3 7 mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 56 amic technology corp. figure 37. word read quad i/o instruction sequence (initial word read quad i/o instruction or previous p4=p0) (spi mode only) (84mhz) 810 91112 13 14 15 instruction (e7h) 01234567 s c 16 17 18 19 20 21 22 23 40 4 0 4 0 40 4 0 4 0 4 51 5 1 5 1 51 5 1 5 1 5 62 6 2 6 2 62 6 2 6 2 6 73 7 3 7 3 73 7 3 7 3 7 a23-16 a15-8 a7-0 dummy byte 1 byte 2 byte 3 io 0 io 1 io 2 io 3 io switches from input to output mode 3 mode 0 figure 38. performance enhance mode reset for fast read quad i/o (spi and qpi mode) s c don t care (spi) ffffffffh (qpi) io 0 01 2 3 5 67 4 ffh (spi) ffffffffh (qpi) don t care (spi) ffffffffh (qpi) don t care (spi) ffffffffh (qpi) io 1 io 2 io 3 mode bit reset for quad i/o mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 57 amic technology corp. figure 39-1. reset sequence (spi mode) s c di command command 66h 99h mode 3 mode 0 mode 3 mode 0 figure 39-2. reset sequence (qpi mode) command s c 66h io[3:0] 99h command t ceh mode 3 mode 0 mode 3 mode 0 figure 40. enable quad i/o sequence s c io 0 io[3:1] 01 23 45 67 35h mode 3 mode 0
A25LQ64 series (july, 2014, version 1.4) 58 amic technology corp. figure 41-1. suspend to read latency program latency : 20us erase latency : 20us read command suspend command [b0] s figure 41-2. resume to read latency tse/tbe/tpp read command resume command [30] s figure 41-3. resume to suspend latency 1ms suspend command [b0] resume command [30] s figure 42. software reset recovery 66 99 t rcr t rcp t rec stand-by mode s mode t rcr : 20us (recovery time from read) t rcp : 20us (recovery time from program) t rec : 12ms (recovery time from erase)
A25LQ64 series (july, 2014, version 1.4) 59 amic technology corp. figure 43. power-up timing time v cc v cc (max) v cc (min) t puw device is fully accessible v wi t vsl read command is allowed program, erase and write commands are ignored chip selection is not allowed note: v cc (max.) is 3.7v and v cc (min.) is 2.6v. table 13. power-up timing and v wi threshold symbol parameter min. max. unit. t vsl (1) v cc (min) to s low (v cc rise time) 100 s t puw (1) time delay to write instruction 300 s v wi (1) command inhibit voltage 2.2 2.4 v note: 1. these parameters are characterized only. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0).
A25LQ64 series (july, 2014, version 1.4) 60 amic technology corp. operating conditions at device power-up and power-down ac timing illustrated in figure 44 and figure 45 are for the supply voltages and the control signals at device power-up and power-down. if the timing in the figures is ignored, the device will not operate correctly. during power-up and power-down, s needs to follow the voltage applied on v cc to keep the device not to be selected. the s can be driven low when v v cc reach v cc (min.) and wait a period of t vsl . figure 44. ac timing at device power-up high impedance v cc (min) v cc gnd s c di do t dvch t chdx msb in lsb in t vr t chsl t slch t shsl t shch t chcl t clch t chsh symbol parameter notes min. max. unit t vr v cc rise time 1 20 500000 s/v notes : 1. sampled, not 100% tested. 2. for ac spec t chsl , t slch , t dvch , t chdx , t shsl , t chsh , t shch , t chcl , t clch in the figure, please refer to "ac characteristics" table.
A25LQ64 series (july, 2014, version 1.4) 61 amic technology corp. figure 45. power-down sequence during power-down, s needs to follow the voltage drop on vcc to avoid mis-operation. v cc s c
A25LQ64 series (july, 2014, version 1.4) 62 amic technology corp. erase and programming performance parameter min. typ. (1) max. (2) unit. write status register cycle time 40 ms sector erase cycle time (4kb) 40 150 ms block erase cycle time (32kb) 80 300 ms block erase cycle time (64kb) 120 500 ms chip erase cycle time 12 25 s byte program time (via page program command) 6 30 s page program time 0.3 0.8/2 (5) ms erase/program cycle 100,000 cycles notes: 1. typical program and erase time assumes the following conditions: 25c, 3.3v, and checker board pattern. 2. under worst conditions of 85c and 2.7v. 3. system-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. the maximum chip programming time is evaluated under the worst conditions of 0c, v cc =3.3v, and 100k cycle with 90% confidence level. 5. the page program time is 0.8ms(max.) after 10k cycling and 2ms(max.) after 100k cycling. latch-up characteristics min. max. input voltage with respect to v ss on all power pins, di, s -1.0v 2 v cc max input voltage with respect to v ss on do -1.0v v cc + 1.0v current -100ma +100ma includes all pins except v cc . test conditions: v cc = 3v, one pin at a time.
A25LQ64 series (july, 2014, version 1.4) 63 amic technology corp. part numbering scheme a25 xx x xx x / x packing blank: for dip8 g: for sop8 in tube q: for tape & reel package type blank = 8-pin dip (300mil) m = 8-pin sop (209mil) n = 16-pin sop (300mil) q4 = 8-pin wson (6*5mm) g = 24-ball bga (6*8mm) device voltage l = 2.7-3.6v device type a25 = amic serial flash device density 64 = 64 mbit package material blank: normal f: pb free quad spi operation q = support quad spi operation blank = do not support quad spi operation x e = fixes qe 1
A25LQ64 series (july, 2014, version 1.4) 64 amic technology corp. ordering information part no. speed (mhz) active read current max. (ma) program/erase current max. (ma) standby current max. ( a) package A25LQ64-f 8 pin pb-free dip (300 mil) A25LQ64m-f 8-pin pb-free sop (209mil) A25LQ64m-fe 8-pin pb-free sop (209mil) A25LQ64n-f 16-pin pb-free sop (300mil) A25LQ64q4-f 8-pin pb-free wson (6*5mm) A25LQ64g-f 104/84 25/20 25 10 24-ball pb-free bga (6*8mm) operating temperature range: -40 c ~ +85 c
A25LQ64 series (july, 2014, version 1.4) 65 amic technology corp. package information p-dip 8l outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.180 - - 4.57 a 1 0.015 - - 0.38 - - a 2 0.128 0.130 0.136 3.25 3.30 3.45 b 0.014 0.018 0.022 0.36 0.46 0.56 b 1 0.050 0.060 0.070 1.27 1.52 1.78 b 2 0.032 0.039 0.046 0.81 0.99 1.17 c 0.008 0.010 0.013 0.20 0.25 0.33 d 0.350 0.360 0.370 8.89 9.14 9.40 e 0.290 0.300 0.315 7.37 7.62 8.00 e 1 0.254 0.260 0.266 6.45 6.60 6.76 e 1 - 0.100 - - 2.54 - l 0.125 - - 3.18 - - e a 0.345 - 0.385 8.76 - 9.78 s 0.016 0.021 0.026 0.41 0.53 0.66 notes: 1. dimension d and e 1 do not include mold flash or protrusions. 2. dimension b 1 does not include dambar protrusion. 3. tolerance: 0.010? (0.25mm) unless otherwise specified.
A25LQ64 series (july, 2014, version 1.4) 66 amic technology corp. package information sop 8l (209mil) outline dimensions unit: mm e 4 1 e b 85 d a 2 a a 1 l e 1 0.25 gage plane seating plane c dimensions in mm symbol min nom max a 1.75 1.95 2.16 a 1 0.05 0.15 0.25 a 2 1.70 1.80 1.91 b 0.35 0.42 0.48 c 0.19 0.20 0.25 d 5.13 5.23 5.33 e 7.70 7.90 8.10 e 1 5.18 5.28 5.38 e 1.27 bsc l 0.50 0.65 0.80 0 - 8 notes: maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads
A25LQ64 series (july, 2014, version 1.4) 67 amic technology corp. package information sop 16l (300mil) outline dimensions unit: inches/mm e 8 1 16 9 a a 1 l seating plane h b d d 0.10 c 0.02 (0.41) x 45 e c o dimensions in inch dimensions in mm symbol min max min max a 0.093 0.104 2.36 2.65 a 1 0.004 0.012 0.10 0.30 b 0.016 typ. 0.41 typ. c 0.008 typ. 0.20 typ. d 0.398 0.413 10.10 10.50 e 0.291 0.299 7.39 7.60 e 0.050 typ. 1.27 typ. h 0.394 0.419 10.01 10.64 l 0.016 0.050 0.40 1.27 0 8 0 8 notes: 1. dimensions ?d? does not include mold flash, protrusions or gate burrs. 2. dimensions ?e? does not include interlead flash, or protrusions.
A25LQ64 series (july, 2014, version 1.4) 68 amic technology corp. package information wson 8l (6 x 5 x 0.8mm) outline dimensions unit: mm/mil 1 4 58 0.25 c 0.25 c e d e 2 d 2 e b 8 l a 1 a 3 a 0.10 // c y c seating plane pin1 id area 5 6 7 14 3 2 c0.30 dimensions in mm dimensions in mil symbol min nom max min nom max a 0.700 0.750 0.800 27.6 29.5 31.5 a 1 0.000 0.020 0.050 0.0 0.8 2.0 a 3 0.203 ref 8.0 ref b 0.350 0.400 0.480 13.8 15.8 18.9 d 5.900 6.000 6.100 232.3 236.2 240.2 d 2 3.200 3.400 3.600 126.0 133.9 141.7 e 4.900 5.000 5.100 192.9 196.9 200.8 e 2 3.800 4.000 4.200 149.6 157.5 165.4 l 0.500 0.600 0.750 19.7 23.6 29.5 e 1.270 bsc 50.0 bsc y 0 - 0.080 0 - 3.2 note: 1. controlling dimension: millimeters 2. leadframe thickness is 0.203mm (8mil)
A25LQ64 series (july, 2014, version 1.4) 69 amic technology corp. package information mini bga 24l (6 x 8mm) outline dimensions unit: inches/mm a 1 a b c d e f top view side view seating plane 12 34 bottom view pin a1 index d a e a 2 0.10 c c pin a1 index e 1 2 3 4 e 1 e d1 a b c d e f b dimensions in inches dimensions in mm symbol min. nom. max. min. nom. max. a - - 0.047 - - 1.20 a 1 0.010 0.012 0.014 0.25 0.30 0.35 a 2 - 0.033 - - 0.85 - b 0.014 0.016 0.018 0.35 0.40 0.45 d 0.313 0.315 0.317 7.95 8.00 8.05 d 1 0.197 bsc 5.00 bsc e 0.039 bsc 1.00 bsc e 0.234 0.236 0.238 5.95 6.00 6.05 e 1 0.118 bsc 3.00 bsc

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